1. Technical Field
This disclosure is directed to integrated circuits (ICs), and more particularly, to delay compensation in data transmissions that occur in ICs.
2. Description of the Related Art
In computers and other electronic systems, data is often transmitted synchronous with a clock signal. For example, data to be written to a memory may be sent from an IC to a memory on another chip along with a clock signal. In another example, data may be transferred within an IC, from a processor core to an on-chip memory, along with a clock signal. During such data transfers, inherent delays in the signal paths for both the data and clock signals can cause timing mismatches at the receiver. Accordingly, compensation circuitry is often provided at the receiver in order to apply delays to ensure data is properly captured.
One common type of circuit used for implementing delays to compensate for timing mismatches is the delay locked loop (DLL). For example, a DLL may be used to delay a clock signal. The delay may be set such that the clock signal changes states relative to the data such that proper setup and hold time requirements are observed at the receiver.